Everything a computer does is essentially following short instructions in the right order. In computing, a single instruction is nothing but a short sequence of code. Latency refers to any delay encountered when one part of a system - in this case, a computer - has to wait on another part of that system to complete a task or instruction.
CAS Latency (CL) is Column Address Strobe Latency. It occurs when the CPU (Central Processing Unit) communicates with the RAM (Random Access Memory). CAS Latency is the amount of time between a request for information reaching the memory column where the information is stored, and information becomes available. Latency is measured in clock cycles.
A clock cycle is a unit used to measure how long it takes the CPU to execute an instruction. A CPU’s clock speed is determined by how many clock cycles it can complete in one second. Completing one clock cycle in one second is equal to one hertz (Hz). So, a processor with a clock speed of 1GHz (gigahertz) can complete 1 billion clock cycles per second.
To better understand what CAS Latency is and why it matters, it’s important to understand a little more about how memory is stored, accessed, and processed.
A computer needs internal memory for storing and retrieving data to do all of the things it’s supposed to do. This internal, or main, memory is made up of chips which are sometimes referred to as Integrated Circuits (IC).
I can be divided into two broad categories: RAM and ROM (Read Only Memory). RAM is volatile memory, meaning it only works if the PC is on, while ROM doesn’t need the power to remember things. This article will focus only on how RAM is stored, accessed, and processed by the CPU.
A memory chip is organized into banks, comprised of rows and columns, like a spreadsheet. The capacity of the individual chip dictates how many rows and columns there are in each module.
RAM is described as random access because the CPU doesn’t have to read a whole row to get the information from a cell in a particular column. In other words, there should be no difference in the time it takes to access information in any (random) cell in any column then it takes to access any other.
The process of requesting information from RAM, finding it, and then sending it back to the CPU involves several steps that must be completed individually and in order. Latency occurs because there is a delay of a few clock cycles between each of these steps. This is the Command Rate (CMD) predetermined by the BIOS (Basic Input/Output System). It reflects the amount of time, in clock cycles, a command must be visible to the memory to make sure it has been “seen” before it can be executed.
Memory chips are accessed via control signals sent from the CPU via the memory controller. There is a delay of 1-2 clock cycles between the selection of the chip (via the CS pin) before an initial command can be issued. The number of clock cycles is denoted with the letter t.
The memory controller issues the RAS (Row Address Strobe) command to open the correct row. However, another delay (tRCD) occurs before the row is activated. Next is the CAS (Column Address Strobe) command, which is issued to select the right column, but, again, there is a delay (TCAS). Then follows another delay between the information being accessed and sent out of the memory to the DQ pins. This is what is known as CAS Latency (CL).
Once the information has been retrieved, the memory controller must deactivate the column and row. This is called the Precharge, and tRP is when the Precharge command and the next Active command can be issued. Adding one more delay to this process is a technical restriction, referred to as tRAS. This is the shortest period of time (in clock cycles) that the row must be open before it can be deactivated again. So, for example, if the wrong row is opened in error, the tRAS dictates the delay that will occur before it can be closed again to find the correct row.
The CPU and RAM communicate through the sending and receiving of memory as bits of information, also known as data transfer. The data transfer rate is how many times the memory module receives information from the CPU and sends it back per second. How quickly this happens depends on several things.
The processor speed, as we explained above, is measured in Hertz (Hz), Megahertz (MHz), or Gigahertz (GHz). The CPU can also be measured in terms of bit size - how many bytes of information it can get from the RAM at any one time. A byte is made up of 8 bits. So a 32-bit 800 MHz processor can access 4 bytes of information at any one time, and it can do that 800 million times per second.
RAM speed is dictated by two things: bus width and bus speed. Bus width represents how many bits of information can be sent to the CPU at one time. Bus speed describes the frequency - i.e., how many times those bits can be sent in one second. A bus cycle reflects the total length of time it takes for those bits to travel from the RAM to the CPU. This is also measured in clock cycles.
If the Command Rate adds a delay between each step of the memory access process, it follows that the maximum CPU and RAM speeds can never be reached. So how do you work out how much latency to expect?
The good news is that your RAM timings - how long it takes to access and retrieve data from RAM - are listed alongside everything else. So they will usually be presented in the format 16-16-16-32, where the first column is your CAS latency. But this isn’t the true latency, which can be calculated as follows:
(CAS Latency / RAM clock speed) x 2000 = latency in nanoseconds (ns)
The short answer is yes. Picture your current RAM as a highway. How many sticks of RAM you have represents the lanes on the highway, while the size of your RAM determines how many vehicles can be in each lane at any one time. The speed of your RAM is the speed limit on the highway.
You could open more lanes on the highway by adding more RAM sticks, which increases the highway’s capacity, but unless you’re changing the speed limit on the road, you won’t make your PC run any faster. To do this, you need to increase the clock speed of your RAM.
Increasing clock speed will always improve performance more than lowering RAM timings or latency, but you still need to take the latency into account. As the examples below show, higher RAM timings (CAS Latency) can still cause higher overall latency even if you increase the RAM clock speeds.
(15 / 2400) x 2000 = 12.5 ns of latency
(15 / 2666) x 2000 = 11.25 ns of latency
(17 / 2666) x 2000 = 12.75 ns of latency
Similarly, just because the first example (CAS 15 and 2400GHz) results in lower true latency than the third example (CAS 17 and 2666GHz) does not mean that it will be faster overall. Again, this is because RAM timings and latency are critical when comparing memory of the same size and speed.
Data is stored in rows and columns within RAM. The CPU accesses the information in each cell by sending electrical signals - or commands - via the Memory Controller. To get to the right information, the Memory Controller must select the correct row, activate it to choose the right column, then retrieve the data before closing everything down again. Each step of this process involves a delay of a few clock seconds, representing the time it takes for the command to be presented and then actioned. CAS Latency (CL) describes one of the delays in this process: Column Address Strobe Latency. It describes how long it takes to access the information in a new column after opening the correct row.